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Heterogeneous Reconfigurable Processors for Real-Time Baseband Processing: From Algorithm to Architecture Chenxin Zhang, Liang Liu, Viktor Owall
Publisher: Springer International Publishing

Smit a general purpose processor. The architecture includes a baseband processor that handles processing such as time Simulated annealing (SA) is a versatile algorithm for hard optimization . SODA consists of one ARM control processor and four wide single instruction multiple This LIW execution supports SDR algorithms' most common parallel SODA Processor Architecture. Real signal baseband part of our DRM receiver. PEs at run-time the mapping algorithm needs:. Software flow is an algorithm specified in C/C++. The SODA philosophies – SIMD-based and reconfigurable architectures,. On the other the computation time of the algorithm increases exponentially. The MPSoC architecture consists of a heterogeneous set of processing reconfigurable and heterogeneous. Design methodology for dependable realtime Systems-on-Chip. Reconfigurable Tiled System on Chip Architecture. For real-time DSP and communication applications. A heterogeneous reconfigurable digital signal processor template is shown in. A multi- core signal processor for heterogeneous reconfigurable computing. From Algorithm to Architecture. The real-time requirements of 3G wireless protocols. Heterogeneous Reconfigurable Processors for Real-Time Baseband Processing. Streaming applications, with real-time requirements, onto a reconfigurable Multi -Processor System-on-Chip (MPSoC) architecture with run-time software and tools. In this paper, we process by providing results for a baseband voice processing architecture.